Method of encoding and decoding multi-bit level data

ABSTRACT

A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims priority to Korean Patent Application No. 10-2008-0040877, filed on Apr. 30, 2008, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

BACKGROUND

1. Technical Field

Exemplary embodiments of the invention relate to encoding and decoding technologies, and more particularly to methods of encoding and decoding multi-bit level data.

2. Discussion of Related Art

An error-correcting code (ECC) or forward error correction (FEC) code is a code in which each data signal conforms to specific rules of construction such that departures from that construction in the received signal can be automatically detected and corrected. Error-correcting codes are used in computer data storage, for example in semiconductor memory devices, and in data transmission of communication systems. The error-correcting code may be encoded along with data (or symbols) to be sent to a receiving device. The encoded data may then be decoded by the receiving device to separate the data from the error-correcting code and the error-correcting code can be used to verify that the data was received without errors.

In a parity scheme, the encoded data may be a combination of parity bits and information bits and data errors may reduced by decoding of the encoded data. For example, in memory cells of multi-bit flash memory devices, data errors may be reduced by using data encoded with the error-correcting codes. However, use of parity bits reduces the number of bits that can be used to store information in each cell. This reduction in the number of information bits for each cell reduces the amount of information that may be stored in the flash memory device.

Thus, there is a need for methods of encoding data with error correction and decoding the data that increase the amount of information stored by the encoded data.

SUMMARY

According to an exemplary embodiment of the present invention, a method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding a (P-M) bit level of the P-bit level. The variables of P and M are natural numbers, P is at least two, and M is less than P.

The determining of the range of the error pattern may include: receiving the transmission symbol from a transmission terminal, and determining the range of the error pattern based on a table where the transmission symbol and the error pattern generated according to the transmission symbol are stored. The transmission terminal may be a host and each operation of the method may be performed in a data storage device. The data storage device may include at least one multilevel cell. Each operation of the method may be performed in a communication system.

The method may be performed when data is written to each of multilevel cells of a semiconductor memory device storing the P-bit level, wherein the excluding encoding of the (P-M) bit level may included in an operation in which the M-bit level of the P-bit level of each of the multilevel cells may be encoded.

The variable M may correspond to [log₂L] where L is the total number of error patterns in the range of the error pattern. The variable M may be the smallest integer that is not less than a result of a calculation of log₂L.

The method may further include generating a mapping table for mapping each of a plurality of transmission symbols to a corresponding P-bit level before the determination. The mapping table may be used to map each decoded P-bit level to a corresponding transmission symbol.

The generating of the mapping table may include setting binary vectors of respective symbols in a same transmission candidate symbol set of the plurality of transmission symbols to be different from each other. The transmission candidate symbol set may be a set of all available transmission symbols with respect to a received symbol considering the error pattern. The binary vector may correspond to the encoded M-bit level of the plurality of multi-bit levels.

The setting of the binary vectors to be different from each other may include converting each of the binary vectors in the same transmission candidate symbol set to a gray code and setting the binary vectors to be different from each other.

The generating of the mapping table may further include minimizing a hamming distance of binary vectors between neighboring transmission symbols of the plurality of transmission symbols.

According to an exemplary embodiment of the present invention, a method of decoding multi-bit level data includes: detecting at least one transmission candidate symbol corresponding to a receiving symbol among a plurality of symbols, decoding an encoded M-bit level among a plurality of multi-bit levels corresponding to the receiving symbol, and selecting an original transmission symbol through decoded information of the encoded M-bit level of at least one of the transmission candidate symbols. The variable M is a natural number.

The detecting of at least one of transmission candidate symbols may include: receiving the receiving symbol from a transmission terminal, and detecting at least one of the transmission candidate symbols corresponding to the receiving symbol based on a table storing at least one transmission candidate symbol with respect to each of a plurality of receiving symbols. The transmission terminal may be a host and each operation of the method may be performed in a data storage device. The data storage device may be a semiconductor memory device. Each operation of the method may be performed in a communication system.

According to an exemplary embodiment of the present invention, a method of writing multi-bit level data to each of G-numbered cells includes: receiving parity bits and information bits to be written to each of the G-numbered cells, storing a corresponding one of the parity bits in the P-bit level of each of H-numbered cells of the G-numbered cells, and storing a corresponding one of the information bits in each P-bit level of each of (G-H) numbered cells if the G-numbered cells. The variables G, P, and H are natural numbers, H is less than G, and P is at least two.

The storing of the information bits may further include encoding an M-bit level of the P-bit level, and excluding encoding a (P-M) bit level of the P-bit levels of each of the (G-H) numbered cells. The variable M is a natural number less than P. A parity bit to decode the encoded M-bit level may be stored in the P-bit level of each of cells corresponding to the H-numbered cells.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram of a semiconductor memory device according to an exemplary embodiment of the present invention;

FIG. 2 is a block diagram of an electronic system according to an exemplary embodiment of the present invention including the semiconductor memory device of FIG. 1;

FIGS. 3A-3J illustrate electronic devices having the electronic system of FIG. 2;

FIG. 4 is a table for explaining an error pattern generated in the semiconductor memory device of FIG. 1;

FIG. 5 illustrates a plurality of cells forming the memory unit of FIG. 1;

FIG. 6 illustrates a method of storing information data and parity data in the cells of FIG. 5 according to an exemplary embodiment of the present invention;

FIG. 7 illustrates a method of storing information data and parity data in the cells of FIG. 5 according to an exemplary embodiment of the present invention;

FIG. 8 is a table showing transmission candidate symbols of receiving symbols received by the controller of FIG. 1;

FIG. 9 is a table of a bit to symbol mapping table stored in the controller of FIG. 1 according to an exemplary embodiment of the present invention;

FIG. 10 is a table of a bit to symbol mapping table stored in the controller of FIG. 1 according to an exemplary embodiment of the present invention;

FIG. 11 is a block diagram of an encoding and decoding system according to an exemplary embodiment of the present inventive invention;

FIG. 12 is a flowchart for explaining a method of encoding multi-bit level data according to an exemplary embodiment of the present invention;

FIG. 13 is a flowchart for explaining a method of decoding multi-bit level data according to an exemplary embodiment of the present invention; and

FIG. 14 is a flowchart for explaining a method of writing multi-bit level data according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, the present invention will be described in detail by explaining exemplary embodiments thereof with reference to the attached drawings. Like reference numerals in the drawings denote like elements.

FIG. 1 is a block diagram of a semiconductor memory device according to an exemplary embodiment of the present invention. FIG. 2 is a block diagram of an electronic system according to an exemplary embodiment of the present invention including the semiconductor memory device of FIG. 1. FIGS. 3A-3J illustrate exemplary electronic devices having the electronic system of FIG. 2.

FIG. 4 is a table for explaining an error pattern generated in the semiconductor memory device of FIG. 1. FIG. 5 illustrates a plurality of cells forming a memory 20 unit of FIG. 1. FIGS. 6 and 7 each illustrate a method of storing information data and parity data in the cells of FIG. 5 according to an exemplary embodiment of the present invention.

FIG. 8 is a table showing transmission candidate symbols of receiving symbols received by a controller 13 of FIG. 1. FIGS. 9 and 10 are examples of bit to symbol mapping tables that may be stored in the controller 13 of FIG. 1 according to an exemplary embodiment of the present invention. Referring to FIGS. 1-10, a semiconductor memory device 10 may include a controller 13 and a memory unit 20. The semiconductor memory device 10 may be a memory card, for example, CompactFlash, Memory Stick, Memory Stick Duo, MultiMedia Card (MMC), Reduced-Size MMC (RS-MMC), Secure Digital (SD) Card, miniSD Card, microSD (TransFlash) Card, SmartMedia Card, or xD-Picture Card.

The semiconductor memory device 10 is electrically connected to a memory slot 48 of FIG. 2 to store data, for example, image data or audio data, output from an electronic circuit unit 44 via a card interface 46 included in a host 5, or transmit the stored data to the electronic circuit unit 44. For example, when the host 5 is a video camera of FIG. 3A, the electronic circuit unit 44 may include a CMOS image sensor (CIS), an image processor, and a digital signal processing unit to transmit the data, for example, image data or audio data, generated by the electronic circuit unit 44 to the semiconductor memory device 10 via the card interface 48.

The semiconductor memory device 10 may be included in the video camera of FIG. 3A, a television of FIG. 3B, an MP3 player of FIG. 3C, a game console of FIG. 3D, an electronic musical instrument of FIG. 3E, a portable terminal of FIG. 3F, a personal computer (PC) of FIG. 3G, a personal digital assistant (PDA) of FIG. 3H, a voice recorder of FIG. 31, or a PC card of FIG. 3J.

The controller 13 may encode at least one of multi-bit level data corresponding to a symbol or data received from the host 5, or store or write the encoded multi-bit level data in or to the memory unit 20. The controller 13 may decode the encoded multi-bit level data stored in the memory unit 20 and transmit a symbol corresponding to the encoded multi-bit level data to the host 5. The controller 13 may include a host interface 12 and an error correction code (ECC) block 14.

The host interface 12 may transmit a command and data output from the host 5 to the ECC block 14 and the data stored in the memory unit 20 to the host 5 via the ECC block 14. The ECC block 14 may encode at least one of the multi-bit level data corresponding to the symbol or data received from the host 5, store or write the encoded multi-bit level data in or to the memory unit 20, decode the encoded multi-bit level data stored in the memory unit 20, and transmit a symbol corresponding to the decoded multi-bit level data to the host 5.

The ECC block 14 may include an encoder 15, a CPU 16, a memory 17, and a decoder 18. The encoder 15 may encode at least one of the multi-bit level data corresponding to the symbol or data received from the host 5, and store or write the encoded multi-bit level data in or to the memory unit 20. The multi-bit level data includes bit levels or pages stored in each of the cells or multilevel cells of the memory unit 20, for example, a multi-bit flash memory. For a Q-decimal multi-bit flash memory, where “Q” is a natural number, for example, 16, the number of multi-bit levels of the multi-bit level data is B, where “B” is a natural number, for example 4.

To encode the multi-bit level data, the encoder 15 may detect the range or number of error patterns based on a transmission symbol received from the host 5 and a table storing the error patterns that may be generated according to the transmission symbol, and encode at least one of the multi-bit levels corresponding to the transmission symbol based on the range or number of the error patterns. The encoder 15 may encode at least one bit level using an ECC algorithm.

A channel of the memory unit 20, for example, a multi-bit flash memory, may generate an error pattern by incorrectly reading other neighboring symbols. For example, when the transmission symbol transmitted by the memory unit 20 is “3” (see FIG. 4), the controller 13 may receive either “3” or any one of “1”, “2”, and “4” as a receiving symbol. In this example, the error patterns that are values obtained by subtracting a value of the transmission symbol from a value of the receiving symbol are “−2”, “−1”, “0” and “1”.

The transmission symbol generated by the memory unit 20 has an error pattern in a limited range or number. For example, FIG. 4 is a table showing error patterns of a receiving symbol according to the transmission symbol generated by the memory unit 20. When each of transmission symbols 0-15 is a Q-decimal symbol where “Q” is a natural number, for example, 16, the transmission symbol “0” has no error and the range or number of error patterns of the other symbols except for the transmission symbols “1”, “2”, and “15” is limited to four, that is, “−2”, “−1”, “0” and “1”.

The encoder 15 may detect the range or number of error patterns referring to the table of FIG. 4 and encode at least one of the multi-bit levels corresponding to the transmission symbol based on the range or number of the error pattern. For example, the encoder 15 may encode only m-bit levels and exclude encoding (b-m)-bit levels of the b-multi-bit level data of each of the n-numbered cells or multilevel cells forming a codeword, as shown in FIG. 5.

When the range or number of error patterns is L, where “L” is a natural number, the encoder 15 may encode only m-bit levels of a plurality of multi-bit levels, where “m” is [log₂L]. The value “m” may also be the minimum integer not less than a calculation result of log₂L. For example, when the range or number of error patterns is four (e.g., “−2”, “−1”, “0” and “1”), the encoder 15 may encode only two bit levels, for example, the 1^(st) page and the 2^(nd) page, of the multi-bit levels, for example, the 1^(st) page through the 4^(th) page of FIG. 6. An average information bit number per cell (Kavg) may correspond to Equation 1 as follows:

$\begin{matrix} {K_{avg} = {{\sum\limits_{i = 1}^{m}\frac{Ki}{n}} + {\left( {b - n} \right).}}} & \left\lbrack {{Equation}\mspace{14mu} 1} \right\rbrack \end{matrix}$

In Equation 1, “Ki” denotes the information bit number of the i^(th) bit level data where “i” is a natural number. A code rate per cell R may correspond to Equation 2 as follows:

R=Kavg/b.   [Equation 2]

The encoder 15 may encode only two bit levels (the 1^(st) page and the 2^(nd) page) of the four bit levels (the 1^(st) through the 4^(th) page) as shown in FIG. 6, when each of the transmission symbols 0-15 is a Q-decimal symbol, where “Q” is a natural number, for example, 16. A code rate per cell R′ and an average information bit number per cell Kavg′ may correspond respectively to Equations 3 and 4 as follows:

R′=(2n+2k)/4n={4k+2(n−k)}/4=k/n+(n−k)/2n,   [Equation 3]

Kavg′=4R′.   [Equation 4]

For example, in the method of encoding the controller 13 according to the present exemplary embodiment, since only some of the bit levels are encoded, the average information bit number per cell may be increased.

A method of distributing cells to store information bits and parity bits that considers the encoded bit level and the un-encoded bit level will be discussed below. The method may include making the number of information bits of a bit level of an un-encoded portion and the number of information bits of a bit level of an encoded portion identical to or different from each other, for each bit level.

The number of wasted cells may be minimized by adjusting the numbers of information bits and parity bits for each bit level. The number of information bits of an un-encoded portion and the number of information bits of an encoded portion may be adjusted to be identical to each other.

For example, of a plurality of G-numbered cells where “G” is a natural number, each having the first through fourth bit levels (the first through fourth pages) as shown in FIG. 7, the encoder 15 may store information bits only in (G-H)-numbered cells, where “H” is a natural number smaller than “G”, and parity bits of the 1^(st) and 2^(nd) pages only in H-numbered cells. The parity bits of the 1^(st) and 2^(nd) pages stored in the H-numbered cells may be used to decode the encoded information bits of each of the first bit level (the 1^(st) page′) and the second bit level (the 2^(nd) page′).

The cells of FIG. 7 have information bits of the same size for each page (or bit level) compared to the cells of FIG. 6. For example, since the first and second bit levels (the 1^(st) and 2^(nd) pages) of each of the a-numbered cells of FIG. 6 include parity bits, the number of cells for storing information is different for each bit level (e.g., each page). However, in the cells of FIG. 7, since the G-numbered cells of the memory unit 20 include only the parity bits of the 1^(st) and 2^(nd) pages needed to decode a particular bit level data, the number of cells to store information is identical for each bit level so that distributing cells to store information bits may be more easily controlled.

The CPU 16 may control the operations of the encoder 15, the memory 17, and the decoder 18. The CPU 16 may generate a mapping table MT1 for mapping each of the transmission symbols (0-16) to a corresponding multi-bit level and store the generated mapping table MT1 in the memory 17.

The mapping table MT1 is used for mapping each decoded multi-bit level to a corresponding transmission symbol as shown in FIG. 9. When a receiving symbol received from the mapping table MT1 is S_(i), it is assumed that a transmission candidate symbol set with respect to the receiving symbol is T(S_(i)). In this example, the transmission candidate symbol set T(S_(i)) is a set of all available transmission symbols that may be received as the symbol S_(i). When the receiving symbol received from the mapping table MT1 is S_(i) and the transmission candidate symbol set with respect to the receiving symbol, for example, S_(i) of FIG. 6, is T(S_(i)), for example, FIG. 8, the receiving symbol S_(i) may be expressed as a binary vector (x_(i)=(x_(i,1), x_(i,2), . . . , x_(i,b))ε{0,1}^(b)) via a mapping between bit and symbol. In an exemplary embodiment of the binary vector x_(i) of the mapping table MT1, the encoded binary vector is expressed as x_(i) ⁽¹)=(x_(i,1), . . . , x_(i,m))ε{0,1}^(m) and the un-encoded binary vector is expressed as x_(i) ⁽²⁾=(x_(i,m+1), . . . , x_(i,b))ε{0,1}^(b-m).

The CPU 15 may set a particular binary vector of each symbol of the same transmission candidate symbol set of the transmission symbols (0-16), to be different from each other. For example, when the transmission candidate symbol set T(S_(i)) is T(s)={S_(i1), S_(i2), . . . , S_(iM)} and M≦L, the CPU 15 may set the encoded binary vector x_(ij) ⁽¹⁾ of S_(ij) and the encoded binary vector x_(ik) ⁽¹⁾ of S_(ik), to be different from each other, with respect to all j's and k's satisfying an inequality that 1≦j≦k≦M. For example, the CPU 15 may set particular binary vectors x₁ and x₂ for the transmission candidate symbol set, for example, “8”, “9”, “10”, and “11” of FIG. 8, for the receiving symbol, for example, “9” of FIG. 8, respectively, to “00”, “10”, “01”, and “11”.

The CPU 15 may set the particular binary vectors to be different from each other by converting each of the particular binary vectors in the same transmission candidate symbol set to a gray code. For example, the CPU 15 converts each of the particular binary vectors x₁ and x₂ for the transmission candidate symbol set, for example, “8”, “9”, “10”, and “11” of FIG. 8, for the receiving symbol, for example, “9” of FIG. 8, to a gray code, thus respectively set to “00”, “10”, “11”, and “01”, like the mapping table MT3 of FIG. 10.

The CPU 15 may minimize a hamming distance of the binary vectors between the neighboring transmission symbols of a plurality of transmission symbols. For example, the CPU 15 can convert each of the particular binary vectors x₁ and x₂ for the transmission candidate symbol set, for example, “8”, “9”, “10”, and “11” of FIG. 8, for the receiving symbol, for example, “9” of FIG. 8, to a gray code, thus respectively set to “00”, “10”, “11”, and “01”, like the mapping table MT3 of FIG. 10.

The semiconductor memory device 10 according to at least one exemplary embodiment converts each particular binary vector in the same transmission candidate symbol set to a gray code and minimizes the hamming distance of binary vectors between the neighboring transmission symbols.

The memory 17 may store the table of FIG. 4 storing the error patterns, the table of FIG. 8 storing transmission candidate symbols for each receiving symbol, and the mapping table MT1 of FIG. 9 or mapping table MT3 of FIG. 10. The decoder 18 may decode the encoded multi-bit level data stored in the memory unit 20 and transmit a symbol corresponding to the decoded multi-bit level data to the host 5. The decoder 18 may perform decoding using a preset ECC algorithm.

The decoder 18 may detect at least one transmission candidate symbol corresponding to a receiving symbol of the transmission candidate symbols, during decoding of the receiving symbols received from the memory unit 20. For example, when the receiving symbol received from the memory unit 20 is 7, the decoder 18 may detect the transmission candidate symbols “6”, “7”, “8”, and “9” from the table of FIG. 8 stored in the memory 17.

The decoder 18 may decode at least one encoded bit level of the multi-bit levels corresponding to the receiving symbol and detect a symbol including at least one decoded bit level of the transmission candidate symbols as a transmission symbol. For example, when the encoder 16 encodes only two bit levels, for example, the 1^(st) and 2^(nd) pages, of the multi-bit levels, for example, the ^(st) through 4^(th) pages of FIG. 6, the decoder 18 may decode only the two bit levels (e.g., the 1^(st) and 2^(nd) pages).

The decoder 18 may detect a symbol including the two decoded bit levels x1 and x2 of the transmission candidate symbols “6”, “7”, “8”, and “9” based on the mapping table MT1 of FIG. 9 as a transmission symbol. For example, decoder 18 may detect the symbol “6” as a transmission symbol when the decoded two bit levels “x1” and “x2” are respectively “0” and “1”. For example, in the semiconductor memory device 10 according to at least one exemplary embodiment, since the encoding and decoding is performed only for a part of bit levels, for example, the 1^(st) and 2^(nd) pages, and not for the overall multi-bit levels, for example, the 1^(st) through 4^(th) pages, the average information bit number per cell may be increased.

When the CPU 16 is configured to use the mapping table MT3 of FIG. 10, decoding errors may be reduced. An exemplary result of decoding according to the mapping table MT1 or MT3 is shown below based on the assumption that a receiving symbol actually received by the decoder 18 is “8”, while the transmission symbol stored in the memory unit 20 and transmitted to the decoder 18 is “6”.

When the decoder 18 performs bit to symbol mapping using the mapping table MT1 of FIG. 9, a binary vector of the receiving symbol is “0110” and a binary vector of the transmission symbol is “0001”. When an error is generated in the “x2” of the two decoded bit levels x1 and x2 so that x⁽¹⁾=(x1, x2)=(0, 1), the finally decoded multi-bit level data is “0110”, which is a 3-bit error.

However, when the decoder 18 performs bit to symbol mapping using the mapping table MT3 of FIG. 10, a binary vector of the receiving symbol is “1110” and a binary vector of the transmission symbol is “0011”. When an error is generated in the “x2” of the two decoded bit levels x1 and x2 so that x⁽¹⁾=(x1, x2)=(0, 1), the finally decoded multi-bit level data is “0110”, which is a 2-bit error. For example, when the decoder 18 uses the mapping table MT3 of FIG. 10, an error generated when decoding fails may be reduced.

The memory unit 20 may store the multi-bit level data encoded by the ECC block 14. The memory unit 20 may be a non-volatile memory device, for example, a multi-bit flash memory device.

FIG. 11 is a block diagram of an encoding and decoding system according to an exemplary embodiment of the present invention. The encoding and decoding system may be implemented in a communication system or a semiconductor memory device. Referring to FIGS. 1 and 11, an encoding/decoding system 100 may include a first outer encoder 110, a first inner encoder 120, a bit to symbol mapping unit 130, a symbol to bit mapping unit 150, second inner decoder 160, and second outer decoder 180. The first outer encoder 110 may encode externally received data using an ECC algorithm. The inner encoder 120 may encode at least one bit level by classifying the encoded data to a plurality of multi-bit levels or data units based on the encoded data output from the outside encoder 110. For example, by using a first bit level encoder 122, the inner encoder 120 may encode the first bit level using the first ECC algorithm and output the encoded first bit level. By using a first bit level encoder 124, the inner encoder 120 may encode the second bit level using the second ECC algorithm and output the encoded second bit level. Further, the inner encoder 120 may output each of the third and fourth bit levels without encoding the third and fourth bit levels.

The bit to symbol mapping unit 130 may receive the encoded first bit level, the encoded second bit level, the third bit level (e.g., un-encoded), and the fourth bit level (e.g., un-encoded) from the inner encoder 120 and perform bit to symbol mapping in units of cells or symbols based on a received multi-bit level. The bit to symbol mapping unit 130 may transmit a result of the mapping to the channel 140, for example, a semiconductor memory device such as a multi-bit flash memory, or a communication channel.

The symbol to bit mapping unit 150 may receive a symbol via the channel 140 and perform symbol to bit mapping on the received symbol to output data corresponding to the first bit level, data corresponding to the second bit level, data corresponding to the third bit level, and data corresponding to the fourth bit level.

The inner decoder 160 may decode the data corresponding to the first bit level and the data corresponding to the second bit level, respectively using the first and second ECC algorithms. For example, by using a first bit level decoder 162, the inner decoder 160 may decode the data corresponding to the first bit level using the first ECC algorithm and output the decoded data. By using a second bit level decoder 164, the inner decoder 160 may decode the data corresponding to the second bit level using the second ECC algorithm and output the decoded data. The inner decoder 160 may output each of the data corresponding to the third bit level and the data corresponding to the fourth bit level, without encoding.

By using a cell unit final decoder 166, the inner decoder 160 may perform bit to symbol mapping in units of cells or symbols based on the data decoded using the first and second ECC algorithms, the data corresponding to the third bit level, and the date corresponding to the fourth bit level, and output decoded bit level data corresponding to the first, second, third, and fourth bit levels. For example, the cell unit final decoder 166 performs bit to symbol mapping in units of cells or channels based on the multi-bit level data received using the mapping table MT1 of FIG. 9 or the mapping table MT3 of FIG. 10 and outputs bit level data corresponding to the mapped symbol.

The outer decoder 180 may receive data corresponding to the bit level data output from the cell unit final decoder 166 and decode the received data to output the decoded data. The first and second ECC algorithms may be different from each other.

FIG. 12 is a flowchart for explaining a method of encoding multi-bit level data according to an exemplary embodiment of the present invention. Referring to FIGS. 1 and 12, the controller 13 receives a transmission symbol from a transmission terminal, for example, the host 5, (S10). The controller 13 detects a range of an error pattern based on a table, for example, the table of FIG. 4, storing a transmission symbol and the error pattern that may be generated according to the transmission symbol (S12). The controller 13 may encode at least one bit level of the multi-bit levels corresponding to the transmission symbol based on the range of error pattern (S14).

FIG. 13 is a flowchart for explaining a method of decoding multi-bit level data according to an exemplary embodiment of the present invention. Referring to FIGS. 1 and 13, the controller 13 detects at least one transmission candidate symbol corresponding to a receiving symbol among the transmission candidate symbols (S20). For example, the controller 13 detects at least one transmission candidate symbol corresponding to the receiving symbol based on the table of FIG. 8 and stores at least one transmission candidate symbol with respect to each of the receiving symbols. The controller 13 decodes at least one encoded bit level of the multi-bit levels of each of at least one transmission candidate (S22). The controller 13 detects a symbol including at least one decoded bit level of the multi-bit level of each of at least one transmission candidate, as a transmission symbol (S24). For example, the controller 13 detects a symbol including at least one decoded bit level of the multi-bit level of each of at least one transmission candidate, as a transmission symbol, based on the mapping table MT1 of FIG. 9 or the mapping table MT3 of FIG. 10.

FIG. 14 is a flowchart for explaining a method of writing multi-bit level data according to an exemplary embodiment of the present invention. Referring to FIGS. 1 and 14, the ECC block 14 receives parity bits and information bits to write to each of the G-numbered cells, where “G” is a natural number, each having a P bit levels, where “P” is a natural number of 2 or more, to write multi-bit level data to each of the G-numbered cells (S30).

The ECC block 14 stores a corresponding one of the parity bits in the P-bit level of each of the H-numbered cells, where “H” is a natural number smaller than G, and a corresponding one of the information bits in each of the P-bit levels of each of the (G-H) numbered cells (S32).

As described above, according to a method of encoding and decoding multi-bit level data according to at least embodiment of the present invention, since only some multi-bit levels are encoded, the average of the information bits for each cell may be increased. Further, bit errors may be reduced even when decoding fails, by using a bit to symbol mapping table employing a gray code or a bit to symbol mapping table that minimizes a hamming distance of binary vectors between the neighboring symbols. In addition, according to a method of writing multi-bit level data according to at least one exemplary embodiment of the present invention, information bits and parity bits are stored considering the encoded bit level and the un-encoded bit level so that cells may be more effectively distributed.

While the present invention has been described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. 

1. A method of encoding multi-bit level data, the method comprising: determining a range of an error pattern generated according to a transmission symbol; encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern; and excluding encoding a (P-M) bit level of the P-bit level, wherein M and P are natural numbers, P is at least two, and M is less than P.
 2. The method of claim 1, wherein the determining of the range of the error pattern comprises: receiving the transmission symbol from a transmission terminal; and determining the range of the error pattern based on a table where the transmission symbol and the error pattern generated according to the transmission symbol are stored.
 3. The method of claim 2, wherein the transmission terminal is a host and each operation of the method is performed in a data storage device.
 4. The method of claim 3, wherein the data storage device comprises at least one multilevel cell.
 5. The method of claim 2, wherein each operation of the method is performed in a communication system.
 6. The method of claim 1, being performed when data is written to each of multilevel cells of a semiconductor memory device storing the P-bit level, wherein the excluding encoding of the (P-M) bit level is included in an operation in which the M-bit level of the P-bit level of each of the multilevel cells is encoded.
 7. The method of claim 1, wherein M corresponds to [log₂L] and L is the total number of error patterns in the range of the error pattern.
 8. The method of claim 1, further comprising generating a mapping table for mapping each of a plurality of transmission symbols to a corresponding P-bit level before the determination, wherein the mapping table is used to map each of decoded P-bit level to a corresponding transmission symbol.
 9. The method of claim 8, wherein the generating of the mapping table comprises setting binary vectors of respective symbols in a same transmission candidate symbol set of the plurality of transmission symbols to be different from each other, wherein the transmission candidate symbol set is a set of all available transmission symbols with respect to a received symbol considering the error pattern.
 10. The method of claim 9, wherein the binary vectors correspond to the encoded M-bit level of the plurality of multi-bit levels.
 11. The method of claim 9, wherein the setting of the binary vectors to be different from each other comprises converting each of the binary vectors in the same transmission candidate symbol set to a gray code and setting the binary vectors to be different from each other.
 12. The method of claim 9, wherein the generating of the mapping table further comprises minimizing a hamming distance of binary vectors between neighboring transmission symbols of the plurality of transmission symbols.
 13. A method of decoding multi-bit level data, the method comprising: detecting at least one transmission candidate symbol corresponding to a receiving symbol among a plurality of symbols; decoding an encoded M-bit level among a plurality of multi-bit levels corresponding to the receiving symbol; and selecting an original transmission symbol using decoded information of the encoded M-bit level of at least one of the transmission candidate symbols, wherein M is a natural number.
 14. The method of claim 13, wherein the detecting at least one transmission candidate symbol comprises: receiving the receiving symbol from a transmission terminal; and detecting at least one of the transmission candidate symbols corresponding to the receiving symbol based on a table storing at least one transmission candidate symbol with respect to each of a plurality of receiving symbols.
 15. The method of claim 14, wherein the transmission terminal is a host and each operation of the method is performed in a data storage device.
 16. The method of claim 15, wherein the data storage device is a semiconductor memory device.
 17. The method of claim 13, wherein each operation of the method is performed in a communication system.
 18. A method of writing multi-bit level data to each of G-numbered cells, the method comprising: receiving parity bits and information bits to be written to each of the plurality of G-numbered cells; storing a corresponding one of the parity bits in a P-bit level of each of H-numbered cells of the G-numbered cells; and storing a corresponding one of the information bits in each P-bit level of each of (G-H) numbered cells of the G-numbered cells, wherein G, P, and H are natural numbers, H is less than G, and P is at least two.
 19. The method of claim 18, wherein the storing of the information bits further comprises: encoding an M-bit level of the P-bit level; and excluding from encoding a (P-M) bit level of the P-bit levels of each of the (G-H) numbered cells, wherein M is a natural number less than P.
 20. The method of claim 19, wherein a parity bit to decode the encoded M-bit level is stored in the P-bit level of each of the H-numbered cells. 